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    • 专利摘要:

    公开号:SE1050298A1
    申请号:SE1050298
    申请日:2010-03-30
    公开日:2011-10-01
    发明作者:Krister Gumaelius
    申请人:Fairchild Semiconductor；
    IPC主号:
    专利说明:

    15 punch-through effect, whereby the depletion region at the base-collector boundary may meet the depletion region at the base-emitter limit if the base region is too thin. The depletion region is a space charge region of the target substrate in which the semiconductor material is depleted on charge carriers.
    Under such circumstances, the collector area is completely shorted to the emitter area and a large current flows between the collector area and the emitter area. Thus, the thickness of the base region for a certain doping concentration is on the one hand preferably thicker to increase the electrical breakdown voltage of the BJT and on the other hand preferably thinner to increase the gain of the BJT.
    Furthermore, the above-mentioned penetration effect, in which the bipolar transistor has virtually no base (or in which the effective base width is operatively reduced to zero), can occur more easily (ie at a lower collector-base voltage) if there are defects at the boundary between the emitter region and the base area.
    In the manufacture of a mesa etched BJT, or other types of semiconductor components comprising a mesa structure or the like, a critical process step is plasma etching (or dry etching) used to form a structure having a vertical or near vertical side wall in a semiconductor material, e.g. silicon carbide (SiC). Dry etching is normally used to design the emitter range and to complete the base-emitter junction.
    However, dry etching can be at a vertical or almost vertical side wall of a semiconductor material, such as e.g. SiC, result in the formation of a ditch at the base of the wall, which can impair the function of the resulting semiconductor component. In the following, the formation of such a ditch will be called the "ditch effect".
    For a BJT, the formation of such a trench at the boundary between the base region and the emitter region may result in the effective thickness of the base region being reduced and not corresponding to the initially thought thickness of the base region deposited or grown on the substrate, thereby resulting in the breakthrough of a high electric field to the top layer Zflfl 1432431 ll IZl / 'WPANSHIÉ AERTRANSIC ABXPKXTÉNTEFÜGE- ETCl-HSEAZl' LJ4668t5 251 * 10251jltïélößššöalransratlon: July 10 15 20 25 30 3 (emitter range) decreases. Thus, the base region of the bipolar transistor must be thick enough to reduce the penetration effect, which, however, reduces the gain of the bipolar transistor. In addition, the material near the top layer can be redistributed and moved to the ditch during subsequent high temperature heat treatment of the semiconductor component.
    The material movement in combination with the ditch can cause uncontrolled doping and poor material quality in a sensitive part of the transistor (eg at the emitter-base junction), whereby the performance of the BJT deteriorates.
    Accordingly, there is a need to provide new kinds of designs for semiconductor components and / or new manufacturing methods which would remedy at least some of the above-mentioned disadvantages and / or enable the creation of semiconductor components with improved properties.
    SUMMARY OF THE INVENTION An object of the present invention is to remedy the above-mentioned disadvantages and difficulties of the prior art and to provide an improved alternative to the above prior art and prior art. In general, it is an object of the present invention to provide a semiconductor device having improved properties. Furthermore, it is an object of the present invention to provide a method for forming a structure in a target substrate for manufacturing a semiconductor component which reduces the above-mentioned penetration effect.
    These and other objects of the present invention are achieved by a method as defined in claim 1 and a semiconductor component as defined in claim 11. Preferred embodiments are defined in the dependent claims.
    According to a first aspect of the present invention, there is provided a method of forming a structure in a target substrate for manufacturing a semiconductor device. The method comprises the step of providing a masking layer on the target substrate and the step of providing a 2011-02-81 i:: gi WVRANSíCï AßvïâAflzšlß AB P, ' T ^ Er ;' T .E: _: ~ i3lš ~ ETCÉrfXSÉ-. Åil fl l-'lêêåöQ fi l 19201_2ifßllööåömfralïsiaticrï dot; Stair-like profile in the masking layer so that the height of a step of the stair-like profile is less than the thickness of the masking layer. Furthermore, the method comprises the step of performing simultaneous anisotropic etching of the masking layer and the target substrate so that a structure having a step-like profile is formed in the target substrate.
    The present invention is based on the insight that etching a vertical or almost vertical wall of a structure in a target substrate can result in a ditch at the base of such a wall, i.e. at the base of the structure (or in other words at the transition between the structure to be designed and the remaining part of the target substrate). In prior art methods, wherein the masking layer does not comprise a step-like profile, the etching is reinforced at the base of the structure formed to form a trench. When using a masking layer having a stair-like profile, i.e. a plurality of steps whose height is less than the thickness of the masking layer, a structure having a step-like profile can be formed in the target substrate by performing anisotropic etching of the masking layer and the target substrate simultaneously. The simultaneous anisotropic etching of the masking layer and the target substrate (ie while the target substrate is etched, the masking layer is also etched) enables the transfer (either in the 1: 1 representation or in some other ratio depending on the etching selectivity between the masking layer and the target substrate) to the stair-like targeting profile. . The method of the present invention is advantageous because it results in a very small (or negligible) ditch effect at each of the steps of the step-like profile of the structure formed in the target substrate. Thus, there is a very small (or negligible) ditch effect at the base of the structure formed in the target substrate. The trench effect at one step of the step-like profile of the structure to be formed in the target substrate is negligible, or at least reduced, since the height of a step at the base from which a trench can be formed, i.e. the height of the masking layer on top of the step to be formed and the height of the step formed in the target substrate decreases compared with prior art methods, 20 '. ï-OZ-Ü It it 21 V XTRANSIC ABVl-PANSIC ÅB PL TENWÉ EÃJGE- E “TCH“ $ E 2'lO46686 2O '-. TO2Oï__1 1G1l5686_ Vfanslatlöï flof, 10 15 20 25 30 5 wherein the height of the vertical ( or almost vertical) the wall at the base of which a ditch is formed corresponds to the total thickness of the masking layer and the height of the wall of the structure formed in the target substrate. Although a negligible ditch effect may occur at one or more steps of the stair-like profile formed in the target substrate, the ditch effect is reduced due to said plurality of steps. In other words, said plurality of steps formed in the masking layer means that each step becomes smaller and shallower compared to a profile having only a steep wall in the masking layer, so that the ditch effect is eliminated or at least reduced.
    Furthermore, the simultaneous etching of the masking layer and the target substrate to form the step-like profile in the target substrate can result in the top corner (or edge) of a step in the step-like profile being rounded (softer), which further reduces the ditch effect at the base of the step. For a step located near the base of the structure, the masking layer is actually removed early in the anisotropic etching process and the initially sharp edge of the step is rounded during the etching.
    The present invention provides a method of forming a structure in a target substrate for manufacturing a semiconductor component with reduced ditch effect. Application of the method according to the present invention for, for example, the manufacture of a BJT, reduces the risk of penetration between the emitter and collector areas. Thus, the method of the present invention is advantageous because it enables the fabrication of semiconductor components with improved properties. The need to compromise in the construction of the semiconductor device, such as e.g. in determining the base area thickness of a BJT, decreases.
    According to one embodiment, the structure formed in the target substrate comprises at least one side wall having a plurality of steps, which is advantageous since it is sufficient in the manufacture of e.g. a BJT, that at least one side wall of the structure comprises the stair-like profile.
    According to one embodiment, the height of a step of the step-like profile in the masking layer corresponds to less than one third of the ZGW in 02-01 ll El / RTRANGIC ABiCl-RANSIC ABïPATENT ' EDGE-- ETCHASEQ (L4l5686 2l) lO2ll-l _2l “f, l46685_“ lranSlätlon doc 10 15 20 25 30 6 the thickness of the masking layer. Use of at least three steps, i.e. if the height of a step of the step-like profile in the masking layer corresponds to less than one third of the thickness of the masking layer, is advantageous because the ditch effect can be reduced more effectively.
    According to one embodiment, the method of the present invention may comprise the steps of providing a top layer on the masking layer and forming a pattern in the top layer to define the planar shape (or area) of the structure to be formed in the target substrate. With these steps, the external dimensions of the structure to be formed in the target substrate, i.e. dimensions of the base of the structure, are determined. The top layer may be a polymer layer, for example a photoresist layer, in which a pattern may be formed by optical photolithography, electron beam lithography, X-ray lithography, ion beam lithography, nanoprint lithography, or any other form of semiconductor lithographic technology. Furthermore, the deposition of a top layer is advantageous as it may be helpful in the step of providing a step-like profile in the masking layer as described below.
    Various manufacturing techniques can be used to design a stair-like profile in a masking layer. According to one embodiment, the step of providing a step-like profile in the masking layer may comprise a sequence of etching steps. In particular, the sequence may comprise steps of isotropic and anisotropic etching. In the following, two advantageous alternatives for providing a stair-like profile in the masking layer are described.
    According to a first alternative, the sequence comprises a step of anisotropic etching for selective etching of the masking layer along an (almost) vertical direction (whereby the material in the top layer in which a pattern is formed is very little affected by the etching step), whereby (the vertical edge of) a step in the masking layer is formed. The sequence may further comprise a step of isotropic etching for etching the material of the masking layer in all (or at least almost all or at least not only vertical) directions, whereby the masking layer is etched laterally below the top layer. Followed by 2lfil l-OQ-Ol ll 21 / 'lïRANšlíl. ~ ^ «' B" '»T . FÄf» | Slí.I ÅBYFJÅTENTVEÜLÉE »ETlÜIF-lïSEïZ104668520' i lšåíllmä 1 O46öåö_ ffan 15âlarlo. An additional step of anisotropic etching for selective etching of the masking layer in a vertical direction, a further step of the masking layer is formed The sequence (of steps with anisotropic etching and steps with isotropic etching) for forming a step of the step-like profile can then be repeated According to the present embodiment, the height of a step of the step-like profile can be determined by parameters in the steps of isotropic and anisotropic etching, and the width of a step of the step-like profile is determined by parameters of the step with isotropic etching.
    According to a second alternative, the sequence may comprise a step of anisotropic etching for selective etching of the masking layer in a (almost) vertical direction (whereby the material in the top layer in which a pattern is formed is very little affected by the etching step), whereby a step in the masking layer is formed . The sequence may then further comprise a step of isotropic etching to etch the material of the top layer in all (or at least almost all or at least not only vertical) directions, thereby reducing the size of the top layer (at least the lateral dimensions). Followed by a further step of anisotropic etching for selective etching of the masking layer in an (almost) vertical direction, a further step is formed in the masking layer. The sequence (step of anisotropic etching of the masking layer and step of isotropic etching of the masking layer) for forming a step of the step-like profile can be repeated until the desired number of steps has been achieved in the masking layer. According to the present embodiment, the sequence may comprise a step of anisotropic etching for defining the height of a step of the step-like profile in the masking layer and a step of isotropic etching for reducing the area (or size) of the top layer, whereby the width of a step in the step-like the profile of the masking layer is determined via subsequent anisotropic etching of the masking layer.
    The second alternative described above for providing a stair-like profile in the masking layer is advantageous because the outer 201 1-02-01 W 2 V VTRfälwSitï ABWRANSMÉ AB ' P, ATENT' = El3 <3E- E lCH SE ': 21104668ö 20l 10201 _21 O46686, __ l ^ rar1slati0h .too 10 15 20 25 30 8 the dimensions of the structure formed in the target substrate are defined by the initial outer dimensions of the pattern designed in the top layer. The external dimensions (or planar shape) of the structure are therefore defined more precisely, which is advantageous with regard to e.g. subsequent manufacture (eg design of metal contacts) for which the position of the structure on the target substrate is preferably known.
    It will be appreciated that the parameters of the etching processes may be varied in a sequence to control the respective heights of the various steps of the step-like profile in the masking layer. The height of a step located closest to the interface between the structure and the remaining part of the substrate, i.e. the height of the step of the stair-like profile which forms the base of the structure is advantageously well determined as it may comprise a critical electronic transition, e.g. the transition between a p-doped layer and an n-doped layer of the semiconductor component. The height of the step can then be determined based on the respective layers of the active layer of the semiconductor component.
    Usually, the masking layer may be a hard mask or the like, which is used in semiconductor manufacturing to resist an etching process during which the material underlying the hard mask is selectively affected more by the etching process than the hard mask. In the present application, the term "selective" means the difference in etching speed between two different materials when they are subjected to the same etching process.
    According to one embodiment, the etching rate for forming the step-like profile in the target substrate by anisotropic etching can be selected to be substantially the same for the target substrate and for the masking layer. At substantially the same etching rate, the step-like profile in the masking layer is transferred to the target substrate in the ratio 1: 1 (or at least almost the ratio 1: 1). The step-like profile of the structure formed in the target substrate thus directly corresponds to the step-like profile initially provided in the masking layer. Alternatively, the etching rate may be selected to be faster for the target substrate than for ziw-cz-cl: v. 21 »fRA> vslc1L ß'rrRAr ~ isa <: ßxalr> rxrrswf'lißoc; The masking layer, such as e.g. with the ratio 2: 1, 3: 1, 4: 1 or the like, whereby the step-like profile in the target substrate is reinforced in comparison with the target profile provided in the masking layer. For example, with the ratio 2: 1, the height of a step of the step-like profile formed in the target substrate is twice as high as the height of the corresponding step of the step-like profile provided in the masking layer.
    Alternatively, the etching rate can be selected to be lower for the target substrate than for the masking layer, e.g. with the ratio 1: 2, 1: 3, 1: 4 or the like, whereby the height of a step in the step-like profile in the target substrate decreases in comparison with the height of the corresponding step of the step-like profile provided in the masking layer.
    According to one embodiment, the masking layer may be a hard mask comprising one or a combination of the materials silica (SiO 2) and silicon nitride (SixNirx). Such materials are advantageous in combination with a target substrate made of e.g. silicon or silicon carbide because both the masking layer and the target substrate can then be etched with the same type of chemical substances (the same type of chemistry) and thus etched at the same time.
    According to a second aspect of the invention, there is provided a semiconductor device comprising a target substrate having a first region made of a first kind of semiconductor material and a second region made of a second kind of semiconductor material. The first and second kinds of semiconductor materials are different and the first and second regions are adjacent to form an active region of the semiconductor device. At the transition between the first and second regions, the semiconductor device comprises a structure having a step-like profile.
    The semiconductor component of the present invention is advantageous because the penetration effect decreases with such a construction, i.e. a structure with a step-like profile arranged in an active area of the semiconductor component. The ditch effect that can occur at the base of the structure during manufacture is reduced. For a bipolar transistor, for example, the thickness of the base region can be chosen more freely, i.e. the thickness can be relatively thin 201 * C201 'l 2 * VRTPANSICI ABäTRAFlSllÉ AEQPATEÅJUEDGE- ETCi-l SEX2l045686 20'i1020121G4668 ^ 5_Translaiion det 10 15 20 25 30 10 to achieve high gain and still provide a relatively high breakdown voltage.
    The semiconductor component can be advantageously manufactured in a target substrate according to a method as defined in any of the above-mentioned embodiments. As mentioned above, the ditch effect at the base of the structure formed in the target substrate decreases and thus the active area of such a semiconductor component is much less affected by the penetration effect. Consequently, a semiconductor component with improved properties can be obtained.
    According to one embodiment, the first region may comprise p-doped material and the second region may comprise n-doped material, or vice versa, thereby forming a pn junction.
    The first and second types of semiconductor materials may differ from each other, e.g. with respect to doping level or doping atoms (which thereby form p-doped or n-doped active layers).
    According to one embodiment, the semiconductor device may comprise one of the group belonging to a bipolar transistor, a diode, a MOSFET transistor, a JF ET transistor, a thyristor or a bipolar transistor with isolated control.
    In particular, with respect to a bipolar transistor (BJT), with the present invention, the thickness of the base region can be reduced to a greater extent than in comparison with prior art bipolar transistors, thereby increasing the current gain of the bipolar transistor while maintaining a relatively high breakdown voltage.
    According to one embodiment, the step of the step-like profile which forms the base of the structure (i.e. the step arranged closest to the interface between the structure and the remaining part of the target substrate) may comprise a part of the first area and a part of the second area, e.g. may be the emitter region and the base region of a bipolar transistor, respectively.
    According to an embodiment of both the first and second aspects of the invention, the target substrate is a semiconductor / wafer or the like (ie a thin wafer of a semiconductor material) comprising one or a combination of 201 MCZ-Oï 'll 21 / WRANSHÄ "ABYTRANSIC ABXPÅTEBITXEIÜGE- ETCrHSE20146 The materials are silicon carbide (SiC), silicon (Si), gallium arsenide (GaAs), indium phosphide (lnP) and gallium nitride (GaN). The target substrate materials are preferably suitable for different semiconductor materials. that the component can be manufactured.
    In the present application, the term "anisotropic" etching means an etching process which is directionally sensitive, i.e. that the etching preferably takes place along a specific direction or within a specific range of directions. Anisotropic etching obtains significant directing action and the etching normally proceeds more rapidly in a vertical direction than in a horizontal direction.
    In the present application, the term "isotropic" etching means an etching process which is the same or almost the same in all (or almost all) directions.
    In the present application, the term "vertical" or "almost vertical" direction means a direction which is substantially perpendicular to the surface of the target substrate.
    Furthermore, for the sake of clarity, in the present application, the "base" or base layer of a transistor is referred to as the "base region" of the semiconductor component or bipolar transistor, whereas in another (more architectural) context, the term "base" is sometimes used to define the lower portion or bottom of the structure.
    Additional objects, features, and advantages of the present invention will become apparent from the following description of preferred embodiments, drawings, and appended claims. One skilled in the art will appreciate that various features of the present invention may be combined to create embodiments other than those described below.
    BRIEF DESCRIPTION OF THE DRAWINGS The above, as well as additional objects, features and advantages of the present invention will become apparent from the following illustrative, non-limiting detailed description of preferred embodiments of the present invention with reference to the accompanying drawings, in which: iZi-III 020! ll 2l VllRANfšllÉ ABVTFJJXNíSlfÉÉ ÅSQFWTÄEÉNTHEÉJCSE- ETfQIl-li lílßßßåšrïfàOï líJBïÉ fl V / É ld fi llšßöömlrafëâlall <a structure 3 shows a structure for a process. Figures 2a-2d show a process flow illustrating a method of providing a step-like profile in a masking layer in accordance with an exemplary embodiment of the present invention, Figures 3a-3d show a process flow illustrating a method of providing a stair-like profile. stair-like profile in a masking layer in accordance with another exemplary embodiment of the present invention. Fig. 4 shows a flow chart of a method of forming a structure in a target substrate in accordance with an exemplary embodiment of the present invention, and Fig. 5 shows a schematic cross-section of a vertical bipolar transistor as an exemplary embodiment of a semiconductor device according to the present invention. . The semiconductor device may be provided in accordance with a method of the present invention.
    All figures are schematic, not necessarily to scale, and generally show only parts necessary to clarify the invention, with other parts being omitted or merely suggested.
    DETAILED DESCRIPTION Referring to Figures 1a-1d, a process flow is illustrated illustrating a method of forming a structure in a target substrate for fabricating a semiconductor device in accordance with an exemplary embodiment of the present invention.
    Figures 1a-1d show a process flow 1000 illustrating an exemplary embodiment of the method of the present invention with a masking layer 120 provided on top of a target substrate 150 (Figure 1a). The masking layer 120 can be deposited or grown on the target substrate 150.
    Deposition of the masking layer 120 on the target substrate 150 is preferred, however, since the target substrate may comprise a number of layers on its top 20 "» 10201 lay Zl V 'illRâNïšlC ABYTRAF-.líšlll Alšäl fi šäïlšßlTïEifßíÉiE6 e'ï2'. Surface, which layers are intended to be used as active layers of the semiconductor component to be manufactured. Growth of the masking layer from the material of the target substrate would otherwise consume at least a portion of the target substrate and thereby the active layers already grown or deposited on top of it. Furthermore, with respect to manufacturing in SiC in particular, it is normally preferred to deposit the masking layer on top of the target substrate since growth of e.g. an oxide as a masking layer can lead to defects at the interface between the oxide and the target substrate.
    Further, the process flow 1000 includes a step of providing a step-like profile 122 in the masking layer 120 (Figure 1b). Examples of process flows for providing the step-like profile 122 in the masking layer 120 will be described with reference to Figures 2a-2d and 3a-3d in the following.
    Further, the process flow 1000 includes a step of performing anisotropic etching of the masking layer 120 and the target substrate 150 simultaneously (Figure 1c).
    During anisotropic etching, the area of the target substrate 150 that is not covered by the masking layer 120 (i.e., directly exposed to the chemicals used in the anisotropic etching process) is removed from the target substrate 150 and a hole is thereby formed in the target substrate 150 in such an area. Due to the direct effect of anisotropic etching, vertical (or almost vertical) side walls are not etched, or at least they are etched very little, thereby forming a hole with vertical (or almost vertical) edges or side walls. Thus, a step of the step-like profile 124 is formed in the target substrate 150. Further, since the masking layer 120 and the target substrate 150 are etched simultaneously and the masking layer 120 has a step-like profile, areas of the target substrate 150 which are initially protected by the masking layer 120 are exposed at the beginning of the anisotropic etching process. for the anisotropic etching process (ie exposed to the chemical substances used in the anisotropic etching process) later during the anisotropic etching process. Then, material of the target substrate 150 in these areas is removed. Figure 1c is a three-dimensional view of the target substrate 150 and 201 l 02--01 * ll Zl / " TRANS | CI ABYTR / XNíšlllfl ABXPÅTEÖ-ÅTKEDG ETCl-1 SE 2ll} 46tâ86 20l lOÅUL LüllêåâtjwTïansatoh; The masking layer 120 during the anisotropic etching wherein some of the steps of the step-like profile provided in the masking layer 120 have been transferred to the target substrate but not all Additional steps of the step-like profile 124 may be formed in the target substrate 150 by further etching the masking layer 120. and the target substrate 150. Accordingly, a step-like profile 124 is formed which includes a plurality of steps in the target substrate 150 (Figure 1d).
    The anisotropic etching process may preferably be selected to etch both the material constituting the masking layer 120 and the material constituting the target substrate 150 so that simultaneous etching of the masking layer 120 and the target substrate 150 is provided. In other words, the masking layer 120 and the target substrate 150 preferably have the same type of chemistry, i.e. that they can be etched with the same type of chemical substances. An example may be a structure formed in a target substrate 150 made of SiC which by means of a masking layer 120 made of SiO 2 and chemical substances comprising gases such as e.g. SFG and 02. It will be appreciated that the choice of the masking layer 120 and the choice of the etching process depend on the material of the target substrate 150.
    The material of the masking layer 120 is selected so that it can react with the same type of chemistry as the target substrate and the etching process is selected to provide the desired anisotropic etching in both the masking layer 120 and the target substrate 150. In particular, SiC as the semiconductor material, different chemicals are used for the various types. SiC (ie 3C-SiC, 6H-SiC or 4H-SiC preferably react with different types of chemical substances).
    The target substrate 150 may be a semiconductor wafer and the method of the present invention may be applied to all kinds of semiconductor materials comprising at least one of the group belonging to silicon carbide (SiC), silicon (Si), gallium arsenide (GaAs), indium phosphide (InP) and gallium nitride (GaN).
    For semiconductor materials such as e.g. silicon carbide (SiC) or gallium arsenide (GaAs), the anisotropic etching process is advantageously a dry etching process, which usually includes plasma etching, reactive ion etching (RIE etching), reactive ion beam etching, sputtering etching, inductive 201 'l 62-01' l 'l 21. / VFRANSIC ABYTRANSlC ÅBëPi-YTENlïEDGE- ETCH SE 21046 {S86 20l 10201 _21046686__Tfanslaticn hidden 10 15 20 25 30 15 coupled plasma etching (ICP etching), electron cyclotron resonance etching (ECR etching). These techniques are usually based on the interaction (physical and / or chemical) between the target substrate and the chemical substances. Examples of reactive gases used in dry etching may be one or a combination of fluorocarbons, oxygen, chlorine gas, boron trichloride, and other gases. With such types of processes, the portions of the masking layer 120 and the target substrate 150 that are exposed to ion irradiation are removed (physically and / or chemically). The anisotropic etching process can also be a wet etching process if it can provide the anisotropy required.
    However, wet etching usually results in isotropic etching. Furthermore, chemically resistant materials, such as SiC and GaAs, react very slowly when wet etched.
    The etching rate for forming the step-like profile in the target substrate by anisotropic etching can be selected to be substantially the same in the target substrate 150 and in the masking layer 120. In such conditions, the step-like profile 122 of the masking layer 120 is transferred to the target substrate 150 by the one-to-one ratio (111). The dimensions of the steps of the step-like profile 124 formed in the target substrate 150 are therefore substantially the same as the dimensions of the steps of the step-like profile 122 provided in the masking layer 120.
    However, the etching speed for forming the step-like profile 124 in the target substrate 150 by anisotropic etching can be chosen to be faster for the target substrate 150 than for the masking layer 120. The difference in etching speed can be characterized by the so-called "se ectivity" of the etching process. such as 2: 1, 3: 1, 4: 1 or the like, or even a number such as 1.5 wherein the material of the target substrate 150 is etched 1.5 times faster than the material of the masking layer 120. In the present example, the selectivity of the etching process reinforces the step-like profile formed in the target substrate 150. The steps of the step-like profile 124 formed in 201l «l) 2 ~ 0'l 11 21 VYFRANSIC ABXTRANSlC ÅB P / ¿ .TENT EDGÉ- ETClt The target substrate 150 is then more pronounced (higher dimensions) than the steps of the stair-like profile provided in the masking layer 120. ../../../../../../../../../../../../../../../../../../../../../../../../../../../../../../../../../../../../../../../../../../../../../../../../../../../../../../../../../../../../../../../../../../../../../../../../../../../../../../../../ ..
    Alternatively, the etching rate for forming the step-like profile 124 in the target substrate 150 by anisotropic etching can be selected to be slower for the target substrate 150 than for the masking layer 120. The difference in etching rate can also be characterized by the selectivity of the etching process, which may e.g. is represented by a ratio such as 1: 2, 1: 3, 1: 4 or the like, or even a number such as 0.33 in which the material of the target substrate 150 is etched approximately three times slower than the material of the masking layer 120. In the present example, the selectivity of the etching process reduces the topography of the step-like profile 124 formed in the target substrate 150. The steps of the step-like profile 124 formed in the target substrate 150 are less pronounced (smaller dimensions) than the steps of the step-like profile 122 provided in the masking layer 120.
    The selectivity of the etching process can be determined by the parameters of the etching process such as the type of chemical, the pressure in the chamber where the etching process takes place, and the temperature. For an etching process based on inductively coupled plasma, the parameters may be the type of chemical, the pressure in the chamber, the power applied to a coil used to accelerate the plasma ions against the target substrate arranged on a so-called plate and the power applied to the plate. For purposes of illustration, the following experimental data, i.e. an anisotropic etching process based on SFS as reactive gas in addition to argon in the volume ratio 3: 1, a pressure of 5 mT, a coil power of 600 W and a plate power of 30 W, at an etching rate of 100 nm / min for a target substrate made of SiC and an etching rate of 95 nm / min for a masking layer made of SiO 2. Under these conditions, the etching rates of the masking layer and the target substrate are substantially the same, and a step-like profile having almost the same dimensions as the step-like profile provided in the masking layer is formed in the target substrate. zoii me: i! : r vwraßrrlsrfc; AawrRANsu: .f » e: PAwfE = ~ ir ^ Eo <; a§_ ET-: Hisiëxz i ozisaseswm 1132 :: i Jag 10 15 20 25 30 17 The resulting structure formed in the target substrate 150 can be defined as a facade structure (or mesa structure if it comprises more than one side wall) comprising a stair-like profile 124. In other words, the structure comprises at least one substantially inclined side wall 126 having a stair-like profile 124. The structure may also be defined by a substantially planar top surface 128 and at least one substantially inclined side wall 126 which includes the stair-like profile 124 (fi gur 1d). Thus, although the angle between the step-like profile step 130 which forms the base of the structure (i.e., the step located closest to the interface between the structure and the remainder of the target substrate 150) and the remaining portion of the target substrate 150 may be a right angle (or an angle close to 90 °) as seen at the local 'step level', the side wall 126 of the structure being substantially inclined from the flat top surface 128 towards the base of the structure so that the step-like profile can be formed. Although Figure 1d shows a structure comprising only a sloping side wall 126 having a stair-like profile, it will be appreciated that the structure may include more than one sloping side wall and that such an additional sloping side wall may also include a stair-like profile. The structure can therefore be substantially symmetrical (about a substantially vertical axis).
    Referring to Figures 2a-2d, a process flow is illustrated illustrating a method of providing a step-like profile in a masking layer in accordance with an exemplary embodiment of the present invention.
    Figures 2a-2d show a process flow 2000 illustrating an exemplary embodiment of the method of the present invention with the top layer 130 provided on the masking layer 120 (Figure 2a). The top layer can e.g. The top layer 130 can then be patterned using lithography techniques such as optical photolithography, electron beam lithography, X-ray lithography, ion beam lithography or nanoprint lithography. top layer 130 Zßl 102431 'li 21 ï / WTRANSNÅT ABKTRANSSIC ABïPATENT EDGE; ETCi-lRSERZl 0466860201 10201 _21 l§46686__T ”anslation don 10 15 20 25 30 18 defines the planar shape of the structure formed in the target substrate the outer 150, i.e. (or the dimensions of the base) of the structure to be formed in the target substrate 150.
    The process flow 2000 further includes a sequence of etching steps. In the present embodiment, the sequence comprises steps for switching between isotropic and anisotropic etching of the masking layer 120. The height of a step of the step-like profile 122 of the masking layer 120 is then defined by parameters of the isotropic and anisotropic etching steps, and the width of a step of the step-like profile 122 of the masking layer 120. defined by the parameters in the step of isotropic etching.
    The process flow 2000 includes a step of anisotropic etching in which the area of the masking layer 120 not covered by the top layer 130 is etched away, i.e. that the material of the masking layer 120 is removed in these exposed areas (Figure 2b). An (almost) vertical edge or wall is then formed in the masking layer 120.
    The process flow 2000 further comprises a step of isotropic etching in which the masking layer 120 is etched in (almost) all directions, i.e. horizontally and vertically, including an area below the top layer 130 (Figure 2c). The previously formed vertical wall is thus moved laterally below the top layer 130.
    Furthermore, the process flow 2000 may include an additional step of anisotropic etching to form an additional vertical wall in the masking layer 120 (Figure 2d). The anisotropic etching step performed in Figure 2d is in principle equivalent to the anisotropic etching step described with reference to Figure 2b. However, different parameters (especially the etching time) can be used if the dimensions of the steps of the stair-like profile are to be different compared to each other. A step is thus formed in the masking layer 120. The above-mentioned sequence of anisotropic etching (Figure 2b) and isotropic etching (Figure 2c) can be repeated until a desired number of steps has been obtained in the masking layer 120. 20 l 'I 02-01 in Y 21 K / T'RANSl'-C ABëTRANE-Slifï ABNÉÅTENTEÜGE- E “fCH SE 2lO46686 2Cl110201v213llon 300 10 15 20 25 30 19 Plasma etching kan e.g. be used for switching between anisotropic etching and isotropic etching of the masking layer 120. In a plasma etching process, the plasma generates reactive substances used for chemical etching of materials in the immediate vicinity of the plasma. If the etching is completely (or almost completely) chemical, the etching tends to be isotropic. However, the chemical reactions with the masking layer can be driven or amplified by the kinetic energy of the incoming ions and in that case the etching tends to be directed, i.e. anisotropic. Thus, by changing the parameters used during plasma etching, the etching process can be switched from isotropic etching to anisotropic etching and vice versa.
    Referring to Figures 3a-3d, there is shown a process flow 3000 illustrating a method of providing a step-like profile 124 in a masking layer 120 in accordance with another exemplary embodiment of the present invention.
    Figures 3a-3d show a process flow 3000 illustrating another exemplary embodiment of the method of the present invention with a top layer 130 provided on the masking layer 120 (Figure 3a).
    The top layer 130 is equivalent and can be provided in a manner similar to the top layer 130 described with reference to Figure 2a. A pattern is formed in the top layer 130 to define the planar shape (or outer dimensions) of the structure which is then to be formed in the target substrate 150.
    The process flow 3000 further comprises a sequence of etching steps. In the present embodiment, the sequence comprises an step of anisotropic etching for etching the masking layer 120 and defining the height of the step of the step-like profile in the masking layer 120. A (almost) vertical wall or edge is thereby formed in the masking layer (Figure 3b).
    The anisotropic etching is selected so that it preferably etches away the masking layer 120 and does not affect (or at least slightly affect) the top layer 130. 201 1-02-01 l 21 V ïTRAlVSlC ABTRANSIC ÅB “». PATENY.'XEDGE ~ ETCH SE 2l0466ö6 2011C201__2lü4öö 10 15 20 25 30 20 Furthermore, the sequence comprises a step of isotropic etching to reduce the size of the top layer 130 (Figure 3c). The isotropic etching is selected so that it preferably etches away (a portion of) the top layer 130 and does not affect (or at least very little) the masking layer 120. The decrease in the size (width) of the top layer 130 defines the width of the next step of the step-like the profile to be formed in the masking layer 120. Since the reduction of the width of the top layer 130 is performed by isotropic etching, the height of the top layer is also reduced. Thus, the initial thickness of the top layer 130 laid on the masking layer 120 is preferably determined by the desired number of steps of the stair-like profile and their respective sizes.
    The process flow 3000 further includes a subsequent step of anisotropic etching of the masking layer 120 so that an additional (almost) vertical wall or edge is formed in the masking layer 120. A step is thus formed in the masking layer 120 (Figure 3d). The above-mentioned sequence (Figures 3b and 3c) can then be repeated until a desired number of steps have been obtained in the masking kit 120.
    The step-like profile 122 provided in the masking layer 120 comprises a plurality of steps, i.e. a sequence of substantially vertical and horizontal edges.
    The step-like profile 122 in the masking layer 120 can advantageously be formed by means of dry etching processes instead of wet etching processes since dry etching processes provide a more accurate position of the step which forms the base of the structure. This facilitates subsequent positioning of other layers (or contacts) on the target substrate. However, wet etching usually results in over-etching and structures with less well-defined edges.
    For a normal thickness of a few micrometers for a plant or deposited masking layer, the number of steps of the step-like profile in the masking layer may be in the order of 2-100, preferably in the order of 3-50 and, more preferably, in the order of 5-30. 201ll32-01 ll 2% VWTRANSlC ABWRANSIC ABPATENTäEDGE- ETCtt SE 2l046686 * -20t10201Aêlüßlöêßfšwfranslatiori doc 10 15 20 25 30 21 The desired number of steps may vary as a function of the total thickness of the masking layer. More specifically, the height of a step (of the step-like profile provided in the masking layer or the step-like profile formed in the target substrate) is preferably constructed to be less than about 300 nm. Even with a fairly vertical edge, it is true that the ditch effect seems to be insignificant if the height of a step is less than 100 nm. In addition, the edge or the top corner of a step can be rounded during the anisotropic etching process (due to ion irradiation), thereby further reducing the ditch effect. Thus, very little ditch effect is observed even for a step having a height of less than 300 nm, preferably less than about 200 nm.
    For example, for a 1 micrometer thick masking layer of SiO 2 deposited on a SiC target substrate, a step-like profile of about 20 steps can be realized. In the present example, the number of steps may preferably be in the range of 5-30.
    It will be appreciated that the various steps of the stair-like profile formed in the target substrate (or masking layer) may vary in size, i.e. two steps of the stair-like profile do not necessarily have the same height and / or the same width. The step that forms the base of the structure can, for example, advantageously be a little wider and higher than subsequent steps (closer to the upper part of the structure).
    In the process flows described above, the masking layer 120 may be a hard mask comprising one or a combination of the materials silica (SiO 2) and silicon nitride (SiXNiX-1), which are examples of materials compatible with e.g. silicon and silicon carbide target substrates. However, the material of the masking layer is not necessarily limited to these specific examples.
    Referring to Figure 4, there is shown a fate diagram of a method of forming a structure in a target substrate in accordance with an exemplary embodiment of the present invention. Although details and parameters of the technological processes used in each of the steps of the flow chart are given as examples in the following, it should be appreciated that 237 'l 02 The method of the present invention is not limited to such details and parameters and is provided for illustrative purposes only. The various parameters in the processes can be selected with regard to the desired structure to be designed or the desired semiconductor component to be manufactured.
    Figure 4 shows a flow chart 4000 in which the starting material or target substrate 150 is a wafer made of a semiconductor material (eg, SiC). A plurality of active layers may have previously been grown or deposited on top of the target substrate 150. In a first step 4100 of the fate diagram 4000, a masking layer 120 is provided on the target substrate 150. As an example, the masking layer 120 may be an approximately 1200 nm thick layer of SiO 2 deposited on the target substrate 150 by plasma enhanced chemical vapor deposition (PECVD).
    At step 4200, a top layer 130 is then provided, e.g. a photoresist, on the masking layer 120. The top layer is then patterned to define the planar shape of the structure to be then formed in the target substrate 150. For example, an approximately 2000 nm thick photoresist layer may be deposited on the masking layer 120. Followed by standard sub-steps involving exposure, development and hard baking of the photoresist layer, a pattern can be formed in the photoresist layer.
    At step 4300, the masking layer is machined to provide a step-like profile in the masking layer, e.g. in accordance with the process flow 2000 described with reference to Figures 2a-2d or the process flow 3000 described with reference to Figures 3a-3d. Using the process flow 3000 described with reference to Figures 3a-3d, for example, a first step of the step-like profile with a height of approximately 166 nm can be formed in the masking layer 120 by means of a reactive ion etching process (RIE process), the plasma comprising CH F3 as reactive gas in combination with O 2, the pressure is about 50 mT and the power is about 125 W, whereby an etching rate of about 37 nm / min 2G * lIOQ-fit li 21 V KTRANSlC lfälïšlllfïfïölßlf] ÅXBVPAYENTXEDGE- ETCH SEl21O46686 2O110201_ A first step of the step-like profile can thus be provided, then a sequence comprising an isotropic RIE process for reducing the size of the photoresist layer by about 100 nm in a lateral direction can be achieved. (horizontal direction) is performed with O 2 as active gas, a pressure of 200 mT and an output of 45 W, whereby an etching speed of approximately 50 nm / min is achieved. anisotropic RIE process for etching a 110 nm vertical step in the masking layer of SiO 2 with CHF 3 as reactive gas in combination with 0; in the volume ratio 10: 1, a pressure of 50 mT, a power of 125 W, whereby an etching speed of approximately 37 nm / min is achieved. For a 110 nm high step, the step of anisotropic etching lasts for a period of about 3 minutes. The sequence can be repeated three times, whereby three additional steps are formed in the masking layer 120.
    Another subsequent sequence comprising an isotropic RIE process for etching the photoresist layer and an anisotropic RIE process for etching the masking layer can be performed with various parameters. Alternatively, only the parameters (or some of the parameters) in one of the etching steps in the sequence can be changed. In the present example, the etching time of the anisotropic RIE process can be changed from 3 to 4 minutes so that an approximately 150 nm high step is formed in the masking layer of SiO 2 (instead of approximately 110 nm as in the previous sequence). This second sequence can be repeated five times, whereby five further steps are formed in the masking layer 120.
    After the step-like profile 122 has been formed in the masking layer 120, the remaining portion of the top layer 130 may optionally be removed from the masking layer 120 at step 4400. For example, the remaining photoresist layer may be removed by photoresist removal (i.e., etching) in O 2.
    At step 4500, the target substrate 150 and the masking layer 120 are processed in accordance with the process flow 1000 described above with reference to Figures 1a-1d, thereby resulting in a structure having a step-like profile 124 formed in the target substrate 150. Also the parameters in the examples described above in connection with figure 1a-1d can be used for 201 'š - OÉ-lš * '11 _21 / WÛRANSILI AB' lifï / ÄNSIC KXBïP.IÄl'ENT EÜlEE- E-fTCl1 SE ¿10ßlöößêQCï 1 } 2ll “ Transfer of the step-like profile provided in the masking layer 120 to the target substrate 150, i.e. an anisotropic etching process based on inductively coupled plasma with SFS as reactive gas in combination with argon in the volume ratio 3: 1, a pressure of 5 mT, a coil power of 600 W and a plate power of 30 W (resulting in an etching rate of 100 nm / min for SiC and an etching rate of 95 nm / min for SiO 2) for 10 min, thereby etching approximately 1000 nm.
    Optionally, the remaining portion of the masking layer 120 may be removed from the target substrate 150 at step 4600. With a masking layer made of SiO 2 as in the present example, the remaining portion of the masking layer 120 may be removed by wet etching, e.g. in an aqueous (buffered) hydrogen fluoride solution (BHF or HF).
    At step 4700, the target substrate (with its structure) can be heat treated at a high temperature to activate the doping atoms of the target substrate 150 active layers. Heat treatment is advantageous because the step-like profile 124 of the structure formed in the target substrate 150 becomes smoother.
    Referring to Figure 5, a schematic cross-section of a semiconductor device in accordance with an embodiment of the present invention is shown.
    Typically, the semiconductor device 500 comprises a target substrate 550 comprising a first region 520 made of a first kind of semiconductor material and a second region 530 made of a second kind of semiconductor material. The first and second kinds of semiconductor materials are different, and the first and second regions 520 and 530 are adjacent to form an active region of the semiconductor device. At the junction between the first and second regions 520 and 530, the semiconductor device comprises a structure having a step-like profile. The first region may comprise β-doped material and the second region may comprise n-doped material, or vice versa.
    More specifically, Figure 5 shows a schematic cross-section of an NPN-type vertical bipolar transistor 500 in accordance with an embodiment of the present invention. The vertical bipolar transistor 500 of NPN type 2011-O2-0l 11 21 'l / NTR / Älüíålll »ålßlTRANSlC ÅB PA' fl" El l "f fšDGE- ETCl-lltSE 2 / l046686 20110201_21O46686_loc15lat: ori A collector region 510, a base region 520 and an emitter region 530 disposed on a target substrate 550, the base region 520 being disposed between the collector region 510 and the emitter region 530. The NPN type vertical bipolar transistor 500 also includes a collector contact 515. for electrical connection of the collector area 510, a base contact 525 for electrical connection of the base area 520 and an emitter contact 535 for electrical connection of the emitter area 530.
    In an exemplary but non-limiting embodiment, a low-resistance n-type doped 3-inch or 4-inch disk of 4H-SiC can be used as a starting material. The component process is based on an epitaxially grown NPN structure wherein the collector region 510 is made of n-doped semiconductor material, the base region 520 is made of a p-doped semiconductor material and the emitter region 530 is made of n-doped semiconductor material. A 1200 V-rated SiC-BJT will preferably have a collector region 510 with a doping concentration in the middle of the 1015 cm -1 region and a thickness in the range of 10-20 μm. For the base region 520, the base doping may be in the middle of the 10 ”cmß range and the thickness in the range 300 nm to 1 μm. For the emitter region 530, the emitter doping may be in the order of 1019 cm -1 and the thickness in the range of 500 nm to 2 μm.
    One of the above-described embodiments of the method of the present invention can be used to design the structure comprising the emitter region 530, the base region 520 and the collector region 510, i.e. to construct the emitter-base junction and to terminate the base-collector junction. An NPN-type vertical layer transistor comprises two pn junctions, one at the boundary between the collector region 510 and the base region 520 and another at the boundary between the base region 520 and the emitter region 530, which are two sensitive (active) regions of a bipolar transistor. It is thus preferable to reduce the ditch effect in these areas. A first structure comprising a stair-like profile 524a may be formed in the target substrate at the boundary between the collector area 510 and the base area 520 and a second structure comprising a stair-like profile 524b may be formed in 2011-02-01 if. 21 V 'ltTR fl NâlC ABYTFMWSIC .ÅBPATENUEDGE- ETCH SE =. 21046686 201102O1_2l046686__Translated: on doc 10 15 20 25 30 26 the target substrate at the boundary between the base region 520 and the emitter region 530.
    The two structures may be formed in the semiconductor device 500 in accordance with any of the above-described exemplary embodiments of the present invention.
    Two separate steps for implanting aluminum ions can then be used to provide low resistive base contacts, and to design a high voltage blocking capability (JTE) extension. The JTE implantation dose is preferably in the order of 1013 cm -1 to obtain improved blocking ability.
    Heat treatment for activation of implanted doping atoms can be performed at temperatures in the range 1600 ° C to 1700 ° C. Surface passivation of the step-like profile 524a (see layer 522 in Figure 5) formed at the boundary between the collector region 510 and the base region 520 and of the step-like profile 524b (see layer 532 in Figure 5) formed at the boundary between the base region 520 and the emitter region 530 can be made by thermal oxidation of SiC under improved conditions to achieve low defect concentrations at the interface between the SiC and the SiO 2 surface passivation layer.
    Ohmic (barrier-free) contacts can be made to the n-type doped emitter and collector regions 510 and 530 by deposition of nickel followed by heat treatment at a temperature in the range 800-1100 ° C. An ohmic contact to the p-type doped base region 520 can be made by heat treating an aluminum (Al) alloy at temperatures in the same range as that used to form the nickel contacts. Al can be deposited on top of the base and emitter contacts 525 and 535, respectively, to reduce the series resistance in the metallization and to allow wire bonding to the top of the chip. A metal system that includes nickel and gold can be deposited on the back of the chip to make it compatible with conventional substrate attachment technology.
    As illustrated in Figure 5, the structure obtained in the target substrate 550 in accordance with any of the above-described exemplary embodiments 2G l-fÉïÉ fin '11 21 V “TRANS-lL / J .åšïïfïïšâNSlíl ..f š3 P /'> l ^ lÉNT“: EQGE ~ ETCIH SE "~ 211É46686“ ~ I2Ül * A125 l _12 lÛ4kšö8É1_Täansi The present invention acts as an active region of the semiconductor device 500. In the present example, the steps of the step-like profile 524b forming the base of the structure comprise a portion of the emitter region 530 and a portion of the base region 520. the method of the present invention for manufacturing such a BJT 500, very small ditch effect is obtained at the base of the structure and the penetration effect is reduced.Construction of a semiconductor component such as a bipolar transistor with a structure comprising a step-like profile at the transition between two active layers (pn junction) is therefore advantageous.
    Accordingly, with the present invention, a BJT can be constructed with a thin base region so that high gain is achieved while maintaining the electrical breakthrough of the BJT at a high level.
    More generally, the steps of the step-like profile 124 forming the base of the structure may comprise a layer made of a first kind of semiconductor material and a part of a layer made of a second kind of semiconductor material. For a diode, the first type of semiconductor material may be a p-doped layer while the second type of semiconductor material may be an n-doped material.
    It will be appreciated that the height of the step at which a pn junction is formed may preferably be well controlled. In the present example, the first step of the structure (ie, the step forming the base of the structure, which is located closest to the interface between the structure and the remainder of the target substrate) comprises a pn junction at the boundary between the base region 520 and the emitter region 530. Although the invention has been described with reference to specific exemplary embodiments thereof, many different changes, modifications, and the like will become apparent to those skilled in the art. The described embodiments are therefore not intended to limit the scope of the invention, as defined by the appended claims. Although reference is often made to SiC in the present application, for example, the target material can be any type of semiconductor material. 20l 102-13 'l * l 21 V RTRÅNSHÉ Åßllrïäähšårll ÅBWÅTEhYRÉÜGE- ETCH'-SE'2ïl'l-4ö68l5 20l l020 * _21 () 4 & šö86, _l'rar = slal: on dot. The use of SiC is, however, advantageous in the manufacture of coupling components due to its high electrical breakthrough field, high thermal conductivity and high bottom operating speed for electrons. SiC is a broadband gap semiconductor and can be used to advantage in the manufacture of components for high-power, high-temperature and high-frequency applications.
    Furthermore, although the present invention has been described with reference to an NPN-type vertical bipolar transistor, for which the method of the present invention is particularly advantageous because it reduces the dike effect and thereby the penetration effect, the present invention can also be applied in the manufacture of semiconductor components such as a diode. a MOSFET transistor, a JFET transistor, a thyristor, an isolated gate bipolar transistor, or the like. ;> _. f1: ln2- «w: i 21 vfarnArvslc Asarrzfxrislf; Aeltmxrlïwtxabce- Erclrseazf waaselzm lazo fl ”z lft> 4« sesfs_r.fansl ~. »Mc
    权利要求:
    Claims (14)
    [1]
    A method of forming a structure in a target substrate (150) for manufacturing a bipolar transistor (100), said method comprising: providing a masking layer (120) on the target substrate (150); providing a step-like profile (122) in the masking layer so that the height of a step of the step-like profile is less than the thickness of the masking layer; and performing simultaneous anisotropic etching of the masking layer and the target substrate so that a structure having a step-like profile (124) is formed in the target substrate, the step-like profile in the target substrate being arranged in an active region of the bipolar transistor.
    [2]
    2.. The method of claim 1, wherein the structure formed in the target substrate comprises at least one side wall (126) having a plurality of steps.
    [3]
    3.. A method according to claim 1 or 2, wherein the height of a step of the step-like profile in the masking layer corresponds to less than one third of the thickness of the masking layer.
    [4]
    4.. The method of any of claims 1-3, further comprising the steps of providing a top layer (130) on the masking layer and forming a pattern in the top layer to define the planar shape of the structure formed in the target substrate.
    [5]
    5.. A method according to any one of claims 1-4, wherein the step of providing a step-like profile in the masking layer comprises a sequence of etching steps. 10 15 20 25 30 35
    [6]
    6.. The method of claim 5, wherein said sequence comprises isotropic and anisotropic etching steps.
    [7]
    7.. A method according to claim 6, wherein the height of a step of the step-like profile is determined by parameters in the steps of isotropic and anisotropic etching, and the width of a step of the step-like profile is determined by parameters of the step of isotropic etching.
    [8]
    8.. A method according to claim 5, wherein said sequence comprises a step of anisotropic etching for determining the height of a step of the step-like profile in the masking layer and a step of isotropic etching for reducing the area of the top layer, whereby the width of a step in the step-like profile in the masking layer is determined via subsequent anisotropic etching of the masking layer.
    [9]
    9.. A method according to any one of the preceding claims, wherein the etching rate for forming the step-like profile in the target substrate by anisotropic etching is selected to be substantially the same for the target substrate and for the masking layer, or to be either faster for the target substrate than for the masking layer, or slower for the target substrate than for the target substrate.
    [10]
    A method according to any one of the preceding claims, wherein the masking layer is a hard mask comprising one or a combination of the materials silica (SiO 2) and silicon nitride (SiXNiM).
    [11]
    A bipolar transistor comprising a target substrate (150, 550) having a first region (520) made of a first kind of semiconductor material and a second region (530) made of a second kind of semiconductor material, said first and second kinds of semiconductor materials being different and said first and second regions are adjacent to form an active region of said bipolar transistor, the bipolar transistor comprising a structure having a step-like profile at the transition between said first and second regions.
    [12]
    The bipolar transistor of claim 11, wherein said first region comprises β-doped material and said second region comprises n-doped material, or vice versa. 5
    [13]
    Bipolar transistor according to any one of claims 11-12, wherein the step of the step-like profile which forms the base of the structure comprises a part of the first region and a part of the second region. 10
    [14]
    A bipolar transistor according to any one of claims 11-13, wherein the target substrate comprises one or a combination of the materials silicon carbide (SiC), silicon (Si), gallium arsenide (GaAs), indium phosphide (InP) and gallium nitride (GaN).
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    同族专利:
    公开号 | 公开日
    SE537101C2|2015-01-07|
    EP2553715A1|2013-02-06|
    CN103026459A|2013-04-03|
    US8748943B2|2014-06-10|
    US20130020611A1|2013-01-24|
    KR20130030258A|2013-03-26|
    WO2011120979A1|2011-10-06|
    EP2553715B1|2015-07-15|
    引用文献:
    公开号 | 申请日 | 公开日 | 申请人 | 专利标题
    US3878008A|1974-02-25|1975-04-15|Us Navy|Method of forming high reliability mesa diode|
    DE3879471T2|1988-04-21|1993-09-16|Ibm|METHOD FOR PRODUCING A PHOTORESIST PATTERN AND APPARATUS THEREFOR.|
    US4957875A|1988-08-01|1990-09-18|International Business Machines Corporation|Vertical bipolar transistor|
    US5236547A|1990-09-25|1993-08-17|Kabushiki Kaisha Toshiba|Method of forming a pattern in semiconductor device manufacturing process|
    US5281500A|1991-09-04|1994-01-25|Micron Technology, Inc.|Method of preventing null formation in phase shifted photomasks|
    US5967795A|1995-08-30|1999-10-19|Asea Brown Boveri Ab|SiC semiconductor device comprising a pn junction with a voltage absorbing edge|
    WO1998034274A1|1997-02-03|1998-08-06|The Whitaker Corporation|Self-aligned process for fabricating a passivating ledge in a heterojunction bipolar transistor|
    US5895269A|1997-12-18|1999-04-20|Advanced Micro Devices, Inc.|Methods for preventing deleterious punch-through during local interconnect formation|
    US6562251B1|2000-07-26|2003-05-13|Aiwa Co., Ltd.|Chemical-mechanical contouring method for forming a contoured surface using a stair-step etch|
    JP2008192857A|2007-02-05|2008-08-21|Toshiba Corp|Nonvolatile semiconductor storage device and manufacturing method therefor|
    SE532625C2|2007-04-11|2010-03-09|Transic Ab|Semiconductor component in silicon carbide|
    TW200843105A|2007-04-25|2008-11-01|Promos Technologies Inc|Vertical transistor and method for preparing the same|
    US8652763B2|2007-07-16|2014-02-18|The Board Of Trustees Of The University Of Illinois|Method for fabricating dual damascene profiles using sub pixel-voting lithography and devices made by same|
    CN101855726B|2007-11-09|2015-09-16|克里公司|There is mesa structure and comprise the power semiconductor of resilient coating of table top step|
    JP5377940B2|2007-12-03|2013-12-25|株式会社半導体エネルギー研究所|Semiconductor device|
    US8003522B2|2007-12-19|2011-08-23|Fairchild Semiconductor Corporation|Method for forming trenches with wide upper portion and narrow lower portion|
    US7759186B2|2008-09-03|2010-07-20|The United States Of America As Represented By The Secretary Of The Navy|Method for fabricating junction termination extension with formation of photosensitive dopant mask to control doping profile and lateral width for high-voltage electronic devices|DE112013000866B4|2012-02-06|2019-09-19|Cree, Inc.|Silicon carbidesemiconductor devices|
    US9337268B2|2011-05-16|2016-05-10|Cree, Inc.|SiC devices with high blocking voltage terminated by a negative bevel|
    US9349797B2|2011-05-16|2016-05-24|Cree, Inc.|SiC devices with high blocking voltage terminated by a negative bevel|
    WO2013107508A1|2012-01-18|2013-07-25|Fairchild Semiconductor Corporation|Bipolar junction transistor with spacer layer and method of manufacturing the same|
    US9240359B2|2013-07-08|2016-01-19|Applied Materials, Inc.|3D NAND staircase CD control by using interferometric endpoint detection|
    JP2015032665A|2013-08-01|2015-02-16|住友電気工業株式会社|Wide bandgap semiconductor device|
    US9425265B2|2013-08-16|2016-08-23|Cree, Inc.|Edge termination technique for high voltage power devices having a negative feature for an improved edge termination structure|
    US9601348B2|2014-03-13|2017-03-21|Taiwan Semiconductor Manufacturing Company, Ltd.|Interconnect structure and method of forming same|
    US9299580B2|2014-08-19|2016-03-29|Applied Materials, Inc.|High aspect ratio plasma etch for 3D NAND semiconductor applications|
    EP3222759A4|2014-11-18|2018-05-30|Kwansei Gakuin Educational Foundation|Surface treatment method for sic substrate|
    US9496250B2|2014-12-08|2016-11-15|Globalfoundries Inc.|Tunable scaling of current gain in bipolar junction transistors|
    法律状态:
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    申请号 | 申请日 | 专利标题
    SE1050298A|SE537101C2|2010-03-30|2010-03-30|Semiconductor Component and Method for Designing a Structure in a Target Substrate for Manufacturing a Semiconductor Component|SE1050298A| SE537101C2|2010-03-30|2010-03-30|Semiconductor Component and Method for Designing a Structure in a Target Substrate for Manufacturing a Semiconductor Component|
    PCT/EP2011/054850| WO2011120979A1|2010-03-30|2011-03-29|Semiconductor device and method of forming a structure in a target substrate for manufacturing a semiconductor device|
    EP11712516.1A| EP2553715B1|2010-03-30|2011-03-29|Semiconductor device and method of forming a staircase structure in a target substrate for manufacturing a semiconductor device|
    CN2011800266048A| CN103026459A|2010-03-30|2011-03-29|Semiconductor device and method of forming a structure in a target substrate for manufacturing a semiconductor device|
    KR1020127028454A| KR20130030258A|2010-03-30|2011-03-29|Semiconductor device and method of forming a structure in a target substrate for manufacturing a semiconductor device|
    US13/629,174| US8748943B2|2010-03-30|2012-09-27|Bipolar junction transistor with stair profile|
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